In SRAMs data is typically stored in cross coupled transistor stages where one or more paths to ground can be selectively switched on or off, while in DRAMs, data is stored in capacitors by the operation of one or more transistors.
An access operation is performed in the same manner for both types of memory, by discharging a path to ground.
A SRAM array comprises a matrix of static memory cells (MC), interconnected with horizontal word lines (WL) and vertical bit lines (BL). The memory cell is connected to the bit lines through transfer gate transistors, the gate of which is connected to the word line. Bit lines are common to all cells located on one column, and constitute column busses with a relatively high capacitance, due to the transmission gate transistors connected in parallel. Read/write operations are performed through these bit lines. Bit lines are pre-charged high to a specific voltage level known as the reference voltage, given by a reference voltage generator thru a coupling circuit. In accessing the static type cells, the cells selected through the word line decoder transfer stored data to bit lines by partially discharging the capacitance of one of the bit lines, thus developing a differential voltage between the two bit lines connected to a selected cell. This voltage difference is sensed by a sense amplifier (SA) and amplified/latched in an appropriate buffer, for subsequent outputting to input/output (I/0) pads of the SRAM where desired.
Thus the next access to the array can only occur after the previously selected bit lines have been restored to the reference voltage. This operation is called "bit line restore". The time required for this operation, or "the restore time", directly influences the cycle time, which is the sum of the access time and the restore time. This restore operation has therefore two disadvantages: first, it increases the memory cycle time, because the restore and access cannot overlap in time, and second it is necessary to charge the bit lines which have a relatively high capacitance.
In systems using dynamic memory cells which require destructive read cycles, data is read from the memory cell by detecting a voltage kick on the column bus as the capacitor of the memory cell is either charged or discharged when addressed.
Therefore there is a general problem in restoring highly capacitive busses or lines in memory circuits. The same reasoning also applies to logic circuits.
As far as SRAMs are concerned, a typical solution is given in the proceedings of the 1985 IEEE/SSCC Digest of Technical papers pp. 62-63 in an article entitled: "A 4.5 ns 256 K CMOS SRAM with Tri-level Word Line" by H. Shinohara et al, and in particular in FIG. 2 which shows a circuit schematic of a RAM including a standard restore circuit. FIG. 1 of the present application is typical of such prior art schemes.
FIG. 1 is a schematic diagram of a circuit 10, which is a portion of a conventional SRAM. Circuit 10 includes a conventional static memory cell MC1 which is part of an array of many such cells arranged in rows and columns in a standard manner. Memory cell MC1 is connected between two bit lines: BL (true) and BL (inverted or complementary bit line), which appear as column busses. Memory cell MC1 is addressed (i.e. enabled) by a row line or word line WL. The latter therefore addresses all the memory cells in one row. Transfer gate transistors mentioned above have not been represented for sake of simplicity. Column busses or bit lines BL and BL are respectively connected to the two arms of a sense amplifier (not represented) as known in the art. Bit lines BL and BL exhibit inherently high stray capacitances referenced C1 and C2 resulting from paralleling a great number of said transfer gate transistors and which increase with the number of cells in a column.
Circuit 10 also includes a restore circuit 11 for pulling up the potential of bit lines BL and BL to the reference voltage. Restore circuit 11 comprises two elementary circuits: a coupling/equalizing circuit 12 and a reference voltage generator 13. Circuit 12 comprises three P-channel transistors P14, P15 and P16, connected between BL and BL, and gated by bit line restore clock BLR. Transistors P14 and P15 are used as coupling transistors. When turned on, they apply the reference voltage available on the reference line RL to the bit lines. On the other hand, the two bit lines BL and BL are also coupled together through transistor P16, so that the charge is equally shared between them. Thus, capacitances C1 and C2 are both charged to the level of the reference voltage. Transistor P16 therefore equalizes the charge of capacitances C1 and C2 and therefore the potential of the bit lines. Thus, transistors P14, P15 and P16 pre-charge the bit lines to the reference voltage, available on reference line RL, during the restore time. In all existing techniques known to the applicant, the reference voltage generator 13 simply consists of a common N channel transistor N17, the gate of which is connected to the drain which, in turn, is connected to a first power supply VH. Transistor N17 operates as a standard static current source, supplying the required current to high value capacitances C1 and C2, connected between the bit lines and a second power supply, in the present case, the ground GND. Transistor N17 is very large in size to avoid a considerable voltage drop on the reference line during the restore time. The reference potential is equal to VH-VT, VT being the threshold voltage of transistor N17.
A conventional solution to the problem of restoring highly capacitive bit lines to a defined reference voltage in a SRAM involves the use of a very stable reference voltage generator. This generator has to be very large to accommodate the required current supply in the bit line capacitances. Transistor N17 must then be designed large enough to generate the adequate pre-charge level on the memory bit lines. It is known to use a transistor with several millimeters of channel width, e.g. 15 mm, and therefore this solution requires considerable space in the design of modern silicon IC's.
If a smaller device were used, the designer would have to reduce the speed of restoration, which would result in a very long restore time. Generally, a compromise is made between speed and space, which results in unsatisfactory specifications.
The operation of the memory circuit shown in FIG. 1, with transistor N17 making such a speed/size compromise will be best understood with reference to the signal waveforms shown in FIG. 2, which illustrates the potential at various points of circuit 10. Before memory cell MC1 is accessed, in the initial state, reference line RL (curve 21, FIG. 2A), bit line BL (curve 23, FIG. 2C) and complement bit line BL (curve 24 for read operation, curve 25 for write operation, FIG. 2D) are all pre-charged to a level of one threshold voltage below the power supply, i.e. VH-VT. The bit line restore clock BLR (curve 22, FIG. 2B), varies between VH and GND (referenced 0). Following an access operation started between times t1 and t2, the potential of reference line RL begins to drop at time t2, due to the current supply to the bit lines. At the same time t2, the bit line restore signal BLR goes down to drive transistors P14 and P15, to provide the current from transistor N17 required to push up the potential of the bit lines (BL and BL) to the reference voltage VH-VT. The restore operation lasts from time t2 to time t3. At time t3, the restore operation is considered finished, all lines, and in particular the reference line, are restored. Just after time t3, the BLR clock signal rises.
In this solution, in which a trade off has been made, say the size of transistor N17 is not large enough to be stable, which means that a significant voltage drop in curve 21 is tolerated, the standard restore time is about 12 ns.
This classic voltage source thus results in a speed disadvantage so as to avoid making transistor N17 excessively large. Because the current flow to charge the bit line capacitances is always limited by design constraints, reference voltage generators of the prior art are never optimal.